Semiconductor chips are manufactured in such a manner that after a plurality of integrated circuits have been formed in a batch mode under semiconductor wafer condition, the semiconductor wafer is cut along scribe lines so as to be divided with respect to each of the integrated circuits. While several wafer cutting methods is conventionally employed, for instance, such a wafer cutting method is known that the wafer is mechanically cut by rotary blades (refer to, for example, patent publication 1); and instead of the mechanical cutting method, another wafer cutting method is known as a method based upon a plasma dicing process in that portions of the wafer which correspond to scribe lines are removed by a plasma etching process so as to divide the wafer (refer to, for example, patent publication 2), and the like.
On the other hand, in stages for manufacturing semiconductor chips, when circuit patterns are formed, test patterns employed in characteristic tests are formed on regions corresponding to the scribe lines; and after functions of these test patterns have been accomplished, these test patterns are cut off, or removed during dicing process. In the example shown in the patent publication 1, prior to the dicing process for cutting the wafer itself, the test patterns have been previously removed by employing the rotary blade having the wider width. As a result, since the entire portion of the test patterns are removed, it is possible to avoid “burrs” of cut planes, which occur when the test patterns are partially cut.
Then, another method indicated in a patent publication 3 has been proposed as to removing of the test patterns in such a case that the plasma dicing process is applied. That is, in this example, a protection sheet is adhered to a circuit forming plane of a semiconductor wafer in such a manner that the protection sheet is contacted to test patterns; subsequently, a plasma etching-purpose mask is formed on a rear plane of the circuit forming plane, and the wafer is cut by a plasma etching process; and then, such a test pattern which has not been removed in the plasma etching process but has been left is released in combination with the protection sheet, and thus, is removed. As a consequence, after the plasma etching process, the side of the circuit forming plane is no longer plasma-ashed in order to remove the mask, and therefore, damages of the circuit forming plane caused by the plasma ashing process can be eliminated.    [Patent Publication 1] JP-A-2001-250800    [Patent Publication 2] JP-A-2005-191039    [Patent Publication 3] JP-A-2006-179768
Moreover, the conventional technical ideas described in the above-explained patent publications contain the following difficult points: That is, in the conventional example disclosed in the patent publication 1, since the cutting works by employing two sorts of the rotary blades are required in the dicing step, a total number of the processing steps is increased, so that the improvement in the productivity is impeded. Also, in the example disclosed in the patent publication 3, while the step for performing the plasma etching process from the side of the rear plane of the wafer is made complex, in such a case that the sizes of the test patterns are large and the test patterns have been formed in such a form that the semiconductor chips located adjacent to each other on the scribe lines are coupled to each other without any gap, the test patterns cannot be removed by performing only such a plasma etching process with employment of the process gas of the fluorine series. As a result, there is such a difficult point as to the general-purpose characteristic that the subject to be removable is limited. As previously explained, in the conventional semiconductor chip manufacturing methods, there is the below-mentioned problem: That is, while the general-purpose characteristic is secured, the test patterns in the dicing step can be hardly removed in a higher efficiency and in simple steps.